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| Final Electrical Specifications LTC3733/LTC3733-1 3-Phase, 5-Bit VID, Buck Controllers for AMD CPUs FEATURES s s s s DESCRIPTIO June 2003 s s s s s s s s s s s s s 3-Phase Controller with Onboard MOSFET Drivers Current Mode Control Ensures Current Sharing Differential Amplifier Accurately Senses VOUT 5% Output Current Matching Optimizes Thermal Performance and Size of Inductors and MOSFETs Reduced Input and Output Capacitance Supports Active Voltage Positioning VID Programmable Output Voltage from 0.8V to 1.55V (AMD OpteronTM CPU) 6-Phase, 90A Operation (Figure 14) Output Power Good Indicator with Adaptive Blanking 210kHz to 530kHz Per Phase, PLL, Fixed Frequency Synchronizable (LTC3733-1) PWM, Stage Shedding or Burst Mode(R) Operation OPTI-LOOP(R) Compensation Minimizes COUT Adjustable Soft-Start Current Ramping Short-Circuit Shutdown Timer with Defeat Option No_CPU Detection 36-Lead Narrow SSOP and 38-Lead (5mm x 7mm) QFN The LTC(R)3733 family are PolyPhase(R) synchronous stepdown switching regulator controllers that drive all N-channel external power MOSFET stages in a phaselockable, fixed frequency architecture. The 3-phase controller drives its output stages with 120 phase separation at frequencies of up to 530kHz per phase to minimize the RMS current dissipated by the ESR of both the input and output filter capacitors. The 3-phase technique effectively triples the fundamental frequency, improving transient response while operating each controller at an optimal frequency for efficiency and ease of thermal design. Light load efficiency is optimized by using a choice of output stage shedding or Burst Mode technology. A differential amplifier provides true remote sensing of both the high and low sides of the output voltage at load points. Soft-start and a defeatable, timed short-circuit shutdown protect the MOSFETs and the load. A foldback current circuit also provides protection for the external MOSFETs under short-circuit or overload conditions. An all-"1" VID detector turns off the regulator after 1s timeout. , LTC and LT are registered trademarks of Linear Technology Corporation. Burst Mode, OPTI-LOOP and PolyPhase are registered trademarks of Linear Technology Corporation. AMD Opteron is a trademark of Advanced Micro Devices, Inc. APPLICATIO S s s High Performance Notebook Computers Servers, Desktop Computers and Workstations TYPICAL APPLICATIO 5V VCC 10F LTC3733-1 BOOST1 BOOST2 BOOST3 0.1F TG1 SW1 BG1 SENSE1+ SENSE1- TG2 SW2 BG2 PGND SENSE2+ SENSE2- TG3 SW3 BG3 SENSE3+ - SENSE3 VIN VIN L1 0.8H D1 0.002 SW3 SW2 SW1 POWER GOOD INDICATOR OPTIONAL SYN IN PGOOD PLLIN PLLFLTR L2 0.8H D2 0.002 5 VID BITS ON/OFF 680pF VID0-VID4 RUN ITH L3 0.8H D3 5k 0.1F SS SGND EAIN IN - IN + 0.002 100pF Figure 1. High Current Triple Phase Step-Down Converter 3733i Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. U + 22F 35V x2 VIN 5V TO 28V VOUT 0.8V TO 1.55V 65A U U + COUT 470F 4V x4 3733 F01 1 LTC3733/LTC3733-1 ABSOLUTE AXI U RATI GS Topside Driver Voltages (BOOSTN) ............ 38V to -0.3V Switch Voltage (SWN)................................... 32V to -5V Boosted Driver Voltage (BOOSTN - SWN) .... 7V to -0.3V Peak Output Current <1ms (TGN, BGN) ..................... 5A Supply Voltage (VCC), PGOOD Pin Voltages ................................................ 7V to -0.3V PLLIN, RUN, SS, PLLFLTR, FCB Voltages ............................. VCC to -0.3V PACKAGE/ORDER I FOR ATIO TOP VIEW VID1 RUN PLLFLTR FCB IN+ IN- DIFFOUT EAIN SGND 1 2 3 4 5 6 7 8 9 36 VID0 35 PGOOD 34 BOOST1 33 TG1 32 SW1 31 BOOST2 30 TG2 29 SW2 28 VCC 27 BG1 26 PGND 25 BG2 24 BG3 23 SW3 22 TG3 21 BOOST3 20 VID4 19 VID3 BOOST1 PGOOD PLLIN VID1 VID0 ORDER PART NUMBER LTC3733CG PLLFLTR 1 FCB 2 IN+ 3 IN - 4 DIFFOUT 5 EAIN 6 SGND 7 SENSE1+ 8 SENSE1- 9 SENSE2+ 10 SENSE2 - 11 SENSE3 - 12 RUN TG1 SENSE1+ 10 SENSE1- 11 SENSE2 + 12 SENSE2 - 13 SENSE3 - 14 SENSE3+ 15 SS 16 ITH 17 VID2 18 VID2 VID3 VID4 G PACKAGE 36-LEAD PLASTIC SSOP TJMAX = 125C, JA = 95C/W UHF PACKAGE 38-LEAD (7mm x 5mm) PLASTIC QFN TJMAX = 125C, JA = 34C/W EXPOSED PAD IS SGND (PIN 39) MUST BE SOLDERED TO PCB Consult LTC Marketing for parts specified with wider operating temperature ranges. ELECTRICAL CHARACTERISTICS SYMBOL VREGULATED VSENSEMAX IMATCH PARAMETER Regulated Voltage at IN+ Maximum Current Sense Threshold Current Match Main Control Loop The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VCC = VRUN = VSS = 5V unless otherwise noted. CONDITIONS (Note 3); VID Code = 10011, VITH = 1.2V q SENSE3 + BOOST3 ITH SS VEAIN = 0.5V, VITH Open, VSENSE1-, VSENSE2-, VSENSE3- = 0.8V, 1.55V Worst-Case Error at VSENSE(MAX) 2 U U W WW U W (Note 1) ITH Voltage ................................................ 2.4V to -0.3V Operating Ambient Temperature Range ....... 0C to 70C Junction Temperature (Note 2) ............................. 125C Storage Temperature Range ..................-65C to 150C Lead Temperature (LTC3733CG) (Soldering, 10 sec) ............................................... 300C TOP VIEW ORDER PART NUMBER LTC3733CUHF-1 31 SW1 30 BOOST2 29 TG2 28 SW2 27 VCC 38 37 36 35 34 33 32 39 26 DRVCC 25 BG1 24 PGND 23 BG2 22 BG3 21 SW3 20 TG3 13 14 15 16 17 18 19 MIN 1.067 1.064 65 62 -5 TYP 1.075 1.075 75 75 MAX 1.083 1.086 85 88 5 UNITS V V mV mV % 3733i q LTC3733/LTC3733-1 ELECTRICAL CHARACTERISTICS SYMBOL VLOADREG PARAMETER Output Voltage Load Regulation The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VCC = VRUN = VSS = 5V unless otherwise noted. CONDITIONS (Note 3) Measured in Servo Loop, ITH Voltage = 1.2V to 0.7V Measured in Servo Loop, ITH Voltage = 1.2V to 2V VCC = 4.5V to 7V ITH = 1.2V, Sink/Source 25A (Note 3) ITH = 1.2V, (gm * ZL, ZL = Series 1k-100k-1nF) q q q MIN TYP 0.1 -0.1 0.03 MAX 0.5 -0.5 3.6 0.62 0.7 4.5 UNITS % % %/V mmho MHz V A V V mA A V A V V A VREFLNREG gm gmOL VFCB IFCB VBINHIBIT UVR IQ Output Voltage Line Regulation Transconductance Amplifier gm Transconductance Amplifier GBW Forced Continuous Threshold FCB Bias Current Burst Inhibit Threshold Undervoltage SS Reset Input DC Supply Current Normal Mode Shutdown RUN Pin ON Threshold Soft-Start Charge Current SS Pin Arming Threshold SS Pin Latch-Off Threshold SS Discharge Current Shutdown Latch Disable Current SENSE Pins Source Current Maximum Duty Factor Top Gate Rise Time Top Gate Fall Time Bottom Gate Rise Time Bottom Gate Fall Time 2.5 0.58 3.05 1.5 0.60 0.2 VFCB = 0.65V Measured at FCB pin VCC Lowered Until the SS Pin is Pulled Low (Note 4) VCC = 5V VRUN = 0V, VID0 to VID4 Open VRUN, Ramping Positive VSS = 1.9V VSS, Ramping Positive Until Short-Circuit Latch-Off is Armed VSS, Ramping Negative Soft-Short Condition VEAIN = 0.375V, VSS = 4.5V VEAIN = 0.375V, VSS = 4.5V SENSE1+, SENSE1-, SENSE2+, SENSE2-, SENSE3+, SENSE3- All Equal 1.2V; Current at Each Pin In Dropout CLOAD = 3300pF CLOAD = 3300pF CLOAD = 3300pF CLOAD = 3300pF 95 -5 1 -0.8 3.3 VCC - 1.5 VCC - 0.7 VCC - 0.3 3.8 2.5 20 1.5 -1.5 3.8 3.3 -1.5 1.5 13 98.5 30 40 30 20 60 60 120 0.8 2 150 90 90 90 90 5 20 100 1.9 -2.5 4.5 VRUN ISS VSSARM VSSLO ISCL ISDLHO ISENSE DFMAX TG tR,tF BG tR, tF TG/BG t1D BG/TG t2D tON(MIN) VIDIL VIDIH VIDPULLUP ATTENERR VPGL IPGOOD VPGTHNEG VPGTHPOS tPGBLNK A A % ns ns ns ns ns ns ns V V k Top Gate Off to Bottom Gate On Delay All Controllers, CLOAD = 3300pF Each Driver Synchronous Switch-On Delay Time Bottom Gate Off to Top Gate On Delay All Controllers, CLOAD = 3300pF Each Driver Top Switch-On Delay Time Minimum On-Time Maximum Low Level Input Voltage Minimum High Level Input Voltage VID0 to VID4 Internal Pull-Up Resistance VID0 to VID4 PGOOD Voltage Output Low PGOOD Output Leakage PGOOD Trip Thesholds VDIFFOUT Ramping Negative VDIFFOUT Ramping Positive Power Good Blanking (Note 6) IPGOOD = 2mA VPGOOD = 5V VDIFFOUT with Respect to Set Output Voltage, VID Code = 10011 PGOOD Goes Low After VUVDLY Delay After VID Changes Outside PGOOD Window -7 7 q Tested with a Square Wave (Note 5) VID Parameters -0.25 0.1 0.25 0.3 1 -10 10 120 -14 14 % V A % % s 3733i Power Good Output Indication 3 LTC3733/LTC3733-1 ELECTRICAL CHARACTERISTICS SYMBOL fNOM fLOW fHIGH RPLLTH RPLL IN IPLL LPF PARAMETER Nominal Frequency Lowest Frequency Highest Frequency PLLIN Input Threshold PLLIN Input Resistance Phase Detector Output Current Sinking Capability Sourcing Capability Controller 2-Controller 1 Phase Controller 3-Controller 1 Phase No-CPU Shutdown Latency Differential Gain Input Offset Voltage Common Mode Input Voltage Range Common Mode Rejection Ratio Output Current Gain Bandwidth Product Slew Rate Maximum High Output Voltage Input Resistance RL = 2k IOUT = 1mA Measured at IN+ Pin 0V < IN+ = IN- < 5V, I OUT = 1mA, Input Referred The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VCC = VRUN = VSS = 5V unless otherwise noted. CONDITIONS VPLLFLTR = 1.2V VPLLFLTR = 0V VPLLFLTR = 2.4V LTC3733-1 Only LTC3733-1 Only LTC3733-1 Only fPLLIN < fOSC fPLLIN > fOSC MIN 310 190 470 TYP 350 210 530 1 50 20 20 120 240 After All VID Bits = "1" 0.5 0.995 = 1mA, Input Referred; Gain = 1 0 50 10 70 40 2 5 VCC - 1.2 VCC - 0.8 80 IN+ = IN- = 1.2V, IOUT 1 1.000 0.5 1.005 5 5 MAX 400 250 620 UNITS kHz kHz kHz V k A A Deg Deg s V/V mV V dB mA MHz V/s V k Oscillator and Phase-Locked Loop RRELPHS No_CPU Detection tNOCPU AV VOS CM CMRR ICL GBP SR VO(MAX) RIN Differential Amplifier Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: TJ is calculated from the ambient temperature TA and power dissipation PD according to the following formula: LTC3733CG: TJ = TA + (PD x 95C/W) LTC3733CUHF-1: TJ = TA + (PD x 34C/W) Note 3: The IC is tested in a feedback loop that includes the differential amplifier in a unity-gain configuration loaded with 100A to ground driving the VID DAC into the error amplifier and servoing the resultant voltage to the midrange point for the error amplifier (VITH = 1.2V). Note 4: Dynamic supply current is higher due to the gate charge being delivered at the switching frequency. See Applications Information. Note 5: The minimum on-time condition corresponds to an inductor peakto-peak ripple current of 40% of IMAX (see minimum on-time considerations in the Applications Information Section). Note 6: ATTENERR specification is in addition to the output voltage accuracy specified at VID code 10011. Note 7: This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed 125C when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature may impair device reliability. 3733i 4 LTC3733/LTC3733-1 PI FU CTIO S VID0 to VID4 (Pins 36, 1, 18, 19, 20/Pins 35, 36, 16, 17, 18): Output Voltage Programming Input Pins. A 150k internal pull-up resistor is provided on each input pin. See Table 1 for details. Do not apply voltage to these pins prior to the application of voltage on the VCC pin. RUN (Pin 2/Pin 37): ON/OFF Control of the LTC3733. PLLFLTR (Pin 3/Pin 1): The phase-locked loop's lowpass filter is tied to this pin. Alternatively, this pin can be driven with an AC or DC voltage source to vary the frequency of the internal oscillator. (Do not apply voltage to this pin prior to the application of voltage on the VCC pin.) FCB (Pin 4/Pin 2): Forced Continuous Control Input. The voltage applied to this pin sets the operating mode of the controller. The forced continuous current mode is active when the applied voltage is less than 0.6V. Burst Mode operation will be active when the pin is allowed to float and a stage shedding mode will be active if the pin is tied to the VCC pin. (Do not apply voltage to this pin prior to the application of voltage on the VCC pin.) IN+, IN- (Pins 5, 6/Pins 3, 4): Inputs to a precision, unitygain differential amplifier with internal precision resistors. This provides true remote sensing of both the positive and negative load terminals for precise output voltage control. DIFFOUT (Pin 7/Pin 5): Output of the Remote Output Voltage Sensing Differential Amplifier. EAIN (Pin 8/Pin 6): This is the input to the error amplifier which compares the VID divided, feedback voltage to the internal 0.6V reference voltage. SGND (Pin 9/Pin 7): Signal Ground. This pin must be routed separately under the IC to the PGND pin and then to the main ground plane. SENSE1+ , SENSE2+, SENSE3 + , SENSE1- , SENSE2-, SENSE3- (Pins 10 to 15/Pins 8 to 13): The Inputs to Each Differential Current Comparator. The ITH pin voltage and built-in offsets between SENSE- and SENSE+ pins, in conjunction with RSENSE, set the current trip threshold level. SS (Pin 16/Pin 14): Combination of Soft-Start and ShortCircuit Detection Timer. A capacitor to ground at this pin sets the ramp time to full current output as well as the time delay prior to an output voltage short-circuit shutdown. A minimum value of 0.01F is recommended on this pin. U U U (G36/QFN) ITH (Pin 17/Pin 15): Error Amplifier Output and Switching Regulator Compensation Point. All three current comparator's thresholds increase with this control voltage. PGND (Pin 26/Pin 24): Driver Power Ground. This pin connects to the sources of the bottom N-channel external MOSFETs and the (-) terminals of CIN. BG1 to BG3 (Pins 27, 25, 24/Pins 25, 23, 22): High Current Gate Drives for Bottom N-Channel MOSFETs. Voltage swing at these pins is from ground to VCC. DRVCC (NA/Pin 26): High Power Supply to Drive the External MOSFET Gates in QFN Package. This pin needs to be closely decoupled to the IC's PGND pin. VCC (Pin 28/Pin 27): Main Supply Pin. This pin supplies the controller circuit power. In the G36 package, it is also the high power supply to drive the external MOSFET gates and this pin needs to be closely decoupled to the IC's PGND pin. SW1 to SW3 (Pins 32, 29, 23/Pins 31, 28, 21): Switch Node Connections to Inductors. Voltage swing at these pins is from a Schottky diode (external) voltage drop below ground to VIN (where VIN is the external MOSFET supply rail). TG1 to TG3 (Pins 33, 30, 22/Pins 32, 29, 20): High Current Gate Drives for Top N-channel MOSFETs. These are the outputs of floating drivers with a voltage swing equal to the boost voltage source superimposed on the switch node voltage SW. BOOST1 to BOOST3 (Pins 34, 31, 21/Pins 33, 30, 19): Positive Supply Pins to the Topside Floating Drivers. Bootstrapped capacitors, charged with external Schottky diodes and a boost voltage source, are connected between the BOOST and SW pins. Voltage swing at the BOOST pins is from boost source voltage (typically VCC) to this boost source voltage + VIN (where VIN is the external MOSFET supply rail). PGOOD (Pin 35/Pin 34): This open-drain output is pulled low when the output voltage is outside the PGOOD tolerance window. PGOOD is blanked during VID transitions for approximately 120s. 3733i 5 LTC3733/LTC3733-1 PI FU CTIO S PLLIN (NA/Pin 38): Synchronization Input to Phase Detector. This pin is internally terminated to SGND with 50k. The phase-locked loop will force the rising top gate signal of controller 1 to be synchronized with the rising edge of the PLLIN signal. This pin is not available in the G36 package. FU CTIO AL DIAGRA PLLIN (LTC3733-1 ONLY) FIN 50k RLP PLLFLTR CLP 2.4V 2.5A OSCILLATOR PHASE DET FCB FCB - + DROP OUT DET RS LATCH S R Q Q 0.6V PGOOD 120s BLANKING VID TRANSITIONS IN- 40k 40k - A1 + - + 0.54V IN+ 40k DIFFOUT 40k I1 R1 6.667k EAIN 0.600V VFB - + + 0.660V - EA 45k 2.4V OV 45k VOUT ITH CC R2 VARIABLE RC 5-BIT VID DECODER 6V 1.5A VCC SHDN RST SHED 0.600V RUN SOFTSTART INTERNAL SUPPLY VREF VCC SGND VCC 5(VFB) + CCC SS RUN 1s NO_CPU 100k VID0 VID1 VID2 VID3 VID4 CSS + 6 W U - + U U U U (G36/QFN) Exposed Pad (NA/Pin 39): Signal Ground. Must be soldered to PCB. CLK1 CLK2 CLK3 VCC BOOST DB VIN DUPLICATE FOR SECOND AND THIRD CONTROLLER CHANNELS 0.66V EAIN BOT FORCE BOT SWITCH LOGIC TOP TG CB + CIN SW VCC (DRVCC IN THE LTC3733-1) BOT BG PGND 0.55V + - B FCB SHDN - + - + - ++ 3mV - I2 VCC + 30k SENSE L SLOPE COMP 5(VFB) - 30k SENSE RSENSE COUT 3733 F02 Figure 2 3733i LTC3733/LTC3733-1 OPERATIO Main Control Loop The IC uses a constant frequency, current mode stepdown architecture. During normal operation, each top MOSFET is turned on each cycle when the oscillator sets the RS latch, and turned off when the main current comparator, I1, resets each RS latch. The peak inductor current at which I1 resets the RS latch is controlled by the voltage on the ITH pin, which is the output of the error amplifier EA. The EAIN pin receives a portion of the voltage feedback signal via the DIFFOUT pin through the internal VID DAC and is compared to the internal reference voltage. When the load current increases, it causes a slight decrease in the EAIN pin voltage relative to the 0.6V reference, which in turn causes the ITH voltage to increase until each inductor's average current matches one third of the new load current (assuming all three current sensing resistors are equal). In Burst Mode operation and stage shedding mode, after each top MOSFET has turned off, the bottom MOSFET is turned on until either the inductor current starts to reverse, as indicated by current comparator I2, or the beginning of the next cycle. The top MOSFET drivers are biased from floating bootstrap capacitor CB, which is normally recharged during each off cycle through an external Schottky diode. When VIN decreases to a voltage close to VOUT, however, the loop may enter dropout and attempt to turn on the top MOSFET continuously. The dropout detector counts the number of oscillator cycles that the bottom MOSFET remains off and periodically forces a brief on period to allow CB to recharge. The main control loop is shut down by pulling the RUN pin low. Releasing RUN allows an internal 1.5A current source to charge soft-start capacitor CSS at the SS pin. The internal ITH voltage is then clamped to the SS voltage when CSS is slowly charged up. This "soft-start" clamping prevents abrupt current from being drawn from the input power source. When the RUN pin is low, all functions are kept in a controlled state. Low Current Operation The FCB pin is a multifunction pin: 1) an analog comparator input to provide regulation for a secondary winding by U (Refer to Functional Diagram) forcing temporary forced PWM operation and 2) a logic input to select between three modes of operation. When the FCB pin voltage is below 0.6V, the controller performs as a continuous, PWM current mode synchronous switching regulator. The top and bottom MOSFETs are alternately turned on to maintain the output voltage independent of direction of inductor current. When the FCB pin is below VCC - 1V but greater than 0.6V, the controller performs as a Burst Mode switching regulator. Burst Mode operation sets a minimum output current level before turning off the top switch and turns off the synchronous MOSFET(s) when the inductor current goes negative. This combination of requirements will, at low current, force the ITH pin below a voltage threshold that will temporarily shut off both output MOSFETs until the output voltage drops slightly. There is a burst comparator having 60mV of hysteresis tied to the ITH pin. This hysteresis results in output signals to the MOSFETs that turn them on for several cycles, followed by a variable "sleep" interval depending upon the load current. The resultant output voltage ripple is held to a very small value by having the hysteretic comparator after the error amplifier gain block. When the FCB pin is tied to the VCC pin, Burst Mode operation is disabled and the forced minimum inductor current requirement is removed. This provides constant frequency, discontinuous current operation over the widest possible output current range. At approximately 10% of maximum designed load current, the second and third output stages are shut off and the first controller alone is active in discontinuous current mode. This "stage shedding" optimizes efficiency by eliminating the gate charging losses and switching losses of the other two output stages. Additional cycles will be skipped when the output load current drops below 1% of maximum designed load current in order to maintain the output voltage. This constant frequency operation is not as efficient as Burst Mode operation at very light loads, but does provide lower noise, constant frequency operating mode down to very light load conditions. Tying the FCB pin to ground will force continuous current operation. This is the least efficient operating mode, but may be desirable in certain applications. The output can 3733i 7 LTC3733/LTC3733-1 OPERATIO source or sink current in this mode. When forcing continuous operation and sinking current, this current will be forced back into the main power supply, potentially boosting the input supply to dangerous voltage levels-- BEWARE! Frequency Synchronization or Setup The phase-locked loop allows the internal oscillator to be synchronized to an external source using the PLLIN pin. The output of the phase detector at the PLLFLTR pin is also the DC frequency control input of the oscillator which operates over a 210kHz to 530kHz range corresponding to a voltage input from 0V to 2.4V. When locked, the PLL aligns the turn on of the top MOSFET to the rising edge of the synchronizing signal. When no frequency information is supplied to the PLLIN pin, PLLFLTR goes low, forcing the oscillator to minimum frequency. A DC source can be applied to the PLLFLTR pin to externally set the desired operating frequency. In the G36 package, the PLLIN pin is not brought out and the PLLFLTR pin is for frequency setup only. Differential Amplifier This amplifier provides true differential output voltage sensing. Sensing both VOUT+ and VOUT- benefits regulation in high current applications and/or applications having electrical interconnection losses. This sensing also isolates the physical power ground from the physical signal ground preventing the possibility of troublesome "ground loops" on the PC layout and prevents voltage errors caused by board-to-board interconnects, particularly helpful in VRM designs. Power Good The PGOOD pin is connected to the drain of an internal MOSFET. The MOSFET is turned on once the output voltage has been away from its nominal value by greater than 10%. The PGOOD signal is blanked for approximately 120s during VID transitions. If a new VID transition occurs before the previous blanking time expires, the timer is reset. 8 U (Refer to Functional Diagram) Short-Circuit Detection The SS capacitor is used initially to limit the inrush current from the input power source. Once the controllers have been given time, as determined by the capacitor on the SS pin, to charge up the output capacitors and provide full load current, the SS capacitor is then used as a shortcircuit timeout circuit. If the output voltage falls to less than 70% of its nominal output voltage, the SS capacitor begins discharging, assuming that the output is in a severe overcurrent and/or short-circuit condition. If the condition lasts for a long enough period, as determined by the size of the SS capacitor, the controller will be shut down until the RUN pin voltage is recycled. This built-in latchoff can be overridden by providing >5A at a compliance of 4V to the SS pin. This current shortens the soft-start period but prevents net discharge of the SS capacitor during a severe overcurrent and/or short-circuit condition. Foldback current limiting is activated when the output voltage falls below 70% of its nominal level whether or not the shortcircuit latchoff circuit is enabled. Foldback current limit can be overridden by clamping the EAIN pin such that the voltage is held above the (70%)(0.6V) or 0.42V level even when the actual output voltage is low. The SS capacitor will be reset if the input voltage, (VCC) is allowed to fall below approximately 4V. The capacitor on the pin will be discharged until the short-circuit arming latch is disarmed. The SS capacitor will attempt to cycle through a normal soft-start ramp up after the VCC supply rises above 4V. This circuit prevents power supply latchoff in the event of input power switching break-before-make situations. No_CPU Detection The LTC3733 detects the presense of CPU by monitoring all VID bits. If an all-"1" condition is detected, the controller acknowledges a No_CPU fault. If this fault condition persists for more than 1s, the SS pin is pulled low and the controller is shut down. 3733i LTC3733/LTC3733-1 APPLICATIO S I FOR ATIO The basic application circuit is shown in Figure 1 on the first page of this data sheet. External component selection is driven by the load requirement, and normally begins with the selection of an inductance value based upon the desired operating frequency, inductor current and output voltage ripple requirements. Once the inductors and operating frequency have been chosen, the current sensing resistors can be calculated. Next, the power MOSFETs and Schottky diodes are selected. Finally, C IN and COUT are selected according to the required voltage ripple requirements. The circuit shown in Figure 1 can be configured for operation up to a MOSFET supply voltage of 28V (limited by the external MOSFETs). Operating Frequency The IC uses a constant frequency architecture with the frequency determined by an internal capacitor. This capacitor is charged by a fixed current plus an additional current which is proportional to the voltage applied to the PLLFLTR pin. Refer to the Phase-Locked Loop and Frequency Synchronization and Setup sections for additional information. A graph for the voltage applied to the PLLFLTR pin versus frequency is given in Figure 3. As the operating frequency is increased the gate charge losses will be higher, reducing efficiency (see Efficiency Considerations). The maximum switching frequency is approximately 530kHz. 550 OPERATING FREQUENCY (kHz) 450 350 250 150 0 0.5 1.0 1.5 2.0 PLLFLTR PIN VOLTAGE (V) 2.5 3733 F03 Figure 3. Operating Frequency vs VPLLFLTR U Inductor Value Calculation and Output Ripple Current The operating frequency and inductor selection are interrelated in that higher operating frequencies allow the use of smaller inductor and capacitor values. So why would anyone ever choose to operate at lower frequencies with larger components? The answer is efficiency. A higher frequency generally results in lower efficiency because of MOSFET gate charge and transition losses. In addition to this basic tradeoff, the effect of inductor value on ripple current and low current operation must also be considered. The PolyPhase approach reduces both input and output ripple currents while optimizing individual output stages to run at a lower fundamental frequency, enhancing efficiency. The inductor value has a direct effect on ripple current. The inductor ripple current IL per individual section, N, decreases with higher inductance or frequency and increases with higher VIN or VOUT: IL = VOUT VOUT 1- fL VIN W UU where f is the individual output stage operating frequency. In a PolyPhase converter, the net ripple current seen by the output capacitor is much smaller than the individual inductor ripple currents due to the ripple cancellation. The details on how to calculate the net output ripple current can be found in Application Note 77. Figure 4 shows the net ripple current seen by the output capacitors for the different phase configurations. The output ripple current is plotted for a fixed output voltage as the duty factor is varied between 10% and 90% on the x-axis. The output ripple current is normalized against the inductor ripple current at zero duty factor. The graph can be used in place of tedious calculations. As shown in Figure 4, the zero output ripple current is obtained when: VOUT k where k = 1, 2, ..., N - 1 = VIN N 3733i 9 LTC3733/LTC3733-1 APPLICATIO S I FOR ATIO So the number of phases used can be selected to minimize the output ripple current and therefore the output ripple voltage at the given input and output voltages. In applications having a highly varying input voltage, additional phases will produce the best results. Accepting larger values of IL allows the use of low inductances but can result in higher output voltage ripple. A reasonable starting point for setting ripple current is IL = 0.4(IOUT)/N, where N is the number of channels and IOUT is the total load current. Remember, the maximum IL occurs at the maximum input voltage. The individual inductor ripple currents are constant determined by the inductor, input and output voltages. 1.0 0.9 0.8 0.7 IO(P-P) VO/fL 1-PHASE 2-PHASE 3-PHASE 4-PHASE 6-PHASE 0.6 0.5 0.4 0.3 0.2 0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 DUTY FACTOR (VOUT/VIN) 0.8 0.9 3733 F04 Figure 4. Normalized Peak Output Current vs Duty Factor [IRMS = 0.3(IO(P-P)] Inductor Core Selection Once the value for L1 to L3 is known, the type of inductor must be selected. High efficiency converters generally cannot afford the core loss found in low cost powdered iron cores, forcing the use of ferrite, molypermalloy or Kool M(R) cores. Actual core loss is independent of core size for a fixed inductor value, but it is very dependent on inductance selected. As inductance increases, core losses go down. Unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase. 10 U Ferrite designs have very low core loss and are preferred at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. Ferrite core material saturates "hard," which means that inductance collapses abruptly when the peak design current is exceeded. This results in an abrupt increase in inductor ripple current and consequent output voltage ripple. Do not allow the core to saturate! Power MOSFET and D1, D2, D3 Selection At least two external power MOSFETs must be selected for each of the three output sections: One N-channel MOSFET for the top (main) switch and one or more N-channel MOSFET(s) for the bottom (synchronous) switch. The number, type and "on" resistance of all MOSFETs selected take into account the voltage step-down ratio as well as the actual position (main or synchronous) in which the MOSFET will be used. A much smaller and much lower input capacitance MOSFET should be used for the top MOSFET in applications that have an output voltage that is less than 1/3 of the input voltage. In applications where VIN >> VOUT, the top MOSFETs' "on" resistance is normally less important for overall efficiency than its input capacitance at operating frequencies above 300kHz. MOSFET manufacturers have designed special purpose devices that provide reasonably low "on" resistance with significantly reduced input capacitance for the main switch application in switching regulators. The peak-to-peak MOSFET gate drive levels are set by the voltage, VCC, requiring the use of logic-level threshold MOSFETs in most applications. Pay close attention to the BVDSS specification for the MOSFETs as well; many of the logic-level MOSFETs are limited to 30V or less. Selection criteria for the power MOSFETs include the "on" resistance RSD(ON), input capacitance, input voltage and maximum output current. MOSFET input capacitance is a combination of several components but can be taken from the typical "gate charge" curve included on most data sheets (Figure 5). The curve is generated by forcing a constant input current Kool M is a registered trademark of Magnetics, Inc. 3733i W UU LTC3733/LTC3733-1 APPLICATIO S I FOR ATIO MILLER EFFECT VGS a QIN CMILLER = (QB - QA)/VDS b VGS V 3733 F05 Figure 5. Gate Charge Characteristic into the gate of a common source, current source loaded stage and then plotting the gate voltage versus time. The initial slope is the effect of the gate-to-source and the gateto-drain capacitance. The flat portion of the curve is the result of the Miller capacitance effect of the drain-tosource capacitance as the drain drops the voltage across the current source load. The upper sloping line is due to the drain-to-gate accumulation capacitance and the gateto-source capacitance. The Miller charge (the increase in coulombs on the horizontal axis from a to b while the curve is flat) is specified for a given VDS drain voltage, but can be adjusted for different VDS voltages by multiplying by the ratio of the application VDS to the curve specified VDS values. A way to estimate the CMILLER term is to take the change in gate charge from points a and b on a manufacturers data sheet and divide by the stated VDS voltage specified. CMILLER is the most important selection criteria for determining the transition loss term in the top MOSFET but is not directly specified on MOSFET data sheets. CRSS and COS are specified sometimes but definitions of these parameters are not included. When the controller is operating in continuous mode the duty cycles for the top and bottom MOSFETs are given by: Main Switch Duty Cycle = VOUT VIN V -V Synchronous Switch Duty Cycle = IN OUT VIN U VIN W UU The power dissipation for the main and synchronous MOSFETs at maximum output current are given by: PMAIN = VOUT IMAX (1 + )RDS(ON) + VIN N I VIN2 MAX (RDR )(CMILLER ) * 2N 1 1 + ( f ) VCC - VTH(MIN) VTH(MIN) 2 2 VDS V -V I PSYNC = IN OUT MAX (1 + )RDS(ON) N VIN where N is the number of output stages, is the temperature dependency of RDS(ON), RDR is the effective top driver resistance (approximately 2 at VGS = VMILLER), VIN is the drain potential and the change in drain potential in the particular application. VTH(MIN) is the data sheet specified typical gate threshold voltage specified in the power MOSFET data sheet. CMILLER is the calculated capacitance using the gate charge curve from the MOSFET data sheet and the technique described above. Both MOSFETs have I2R losses while the topside N-channel equation includes an additional term for transition losses, which peak at the highest input voltage. For VIN < 12V, the high current efficiency generally improves with larger MOSFETs, while for VIN > 12V, the transition losses rapidly increase to the point that the use of a higher RDS(ON) device with lower CRSS actually provides higher efficiency. The synchronous MOSFET losses are greatest at high input voltage when the top switch duty factor is low or during a short circuit when the synchronous switch is on close to 100% of the period. The term (1 + ) is generally given for a MOSFET in the form of a normalized RDS(ON) vs temperature curve, but 3733i 11 LTC3733/LTC3733-1 APPLICATIO S I FOR ATIO = 0.005/C can be used as an approximation for low voltage MOSFETs. The Schottky diodes, D1 to D3 shown in Figure 1 conduct during the dead time between the conduction of the two large power MOSFETs. This prevents the body diode of the bottom MOSFET from turning on, storing charge during the dead time and requiring a reverse recovery period which could cost as much as several percent in efficiency. A 2A to 8A Schottky is generally a good compromise for both regions of operation due to the relatively small average current. Larger diodes result in additional transition losses due to their larger junction capacitance. CIN and COUT Selection Input capacitance ESR requirements and efficiency losses are reduced substantially in a multiphase architecture because the peak current drawn from the input capacitor is effectively divided by the number of phases used and power loss is proportional to the RMS current squared. A 3-stage, single output voltage implementation can reduce input path power loss by 90%. In continuous mode, the source current of each top N-channel MOSFET is a square wave of duty cycle VOUT/VIN. A low ESR input capacitor sized for the maximum RMS current must be used. The details of a close form equation can be found in Application Note 77. Figure 6 shows the input capacitor ripple current for different phase configurations with the output voltage fixed and input voltage varied. The input ripple current is normalized against the DC output current. The graph can be used in place of tedious calculations. The minimum input ripple current can be achieved when the product of phase number and output voltage, N(VOUT), is approximately equal to the input voltage VIN or: VOUT k = where k = 1, 2, ..., N - 1 VIN N RMS INPUT RIPPLE CURRNET DC LOAD CURRENT 12 U So the phase number can be chosen to minimize the input capacitor size for the given input and output voltages. In the graph of Figure 6, the local maximum input RMS capacitor currents are reached when: W UU VOUT 2k - 1 where k = 1, 2, ..., N = VIN N These worst-case conditions are commonly used for design because even significant deviations do not offer much relief. Note that capacitor manufacturer's ripple current ratings are often based on only 2000 hours of life. This makes it advisable to further derate the capacitor or to choose a capacitor rated at a higher temperature than required. Several capacitors may also be paralleled to meet size or height requirements in the design. Always consult the capacitor manufacturer if there is any question. The Figure 6 graph shows that the peak RMS input current is reduced linearly, inversely proportional to the number N of stages used. It is important to note that the efficiency loss is proportional to the input RMS current squared and therefore a 3-stage implementation results in 90% less power loss when compared to a single phase design. Battery/input protection fuse resistance (if used), PC 0.6 0.5 0.4 0.3 0.2 0.1 0 1-PHASE 2-PHASE 3-PHASE 4-PHASE 6-PHASE 0.1 0.2 0.3 0.4 0.5 0.6 0.7 DUTY FACTOR (VOUT/VIN) 0.8 0.9 3733 F06 Figure 6. Normalized Input RMS Ripple Current vs Duty Factor for One to Six Output Stages 3733i LTC3733/LTC3733-1 APPLICATIO S I FOR ATIO board trace and connector resistance losses are also reduced by the reduction of the input ripple current in a PolyPhase system. The required amount of input capacitance is further reduced by the factor, N, due to the effective increase in the frequency of the current pulses. Ceramic capacitors are becoming very popular for small designs but several cautions should be observed. "X7R", "X5R" and "Y5V" are examples of a few of the ceramic materials used as the dielectric layer, and these different dielectrics have very different effect on the capacitance value due to the voltage and temperature conditions applied. Physically, if the capacitance value changes due to applied voltage change, there is a concommitant piezo effect which results in radiating sound! A load that draws varying current at an audible rate may cause an attendant varying input voltage on a ceramic capacitor, resulting in an audible signal. A secondary issue relates to the energy flowing back into a ceramic capacitor whose capacitance value is being reduced by the increasing charge. The voltage can increase at a considerably higher rate than the constant current being supplied because the capacitance value is decreasing as the voltage is increasing! Ceramic capacitors, when properly selected and used however, can provide the lowest overall loss due to their extremely low ESR. The selection of COUT is driven by the required effective series resistance (ESR). Typically once the ESR requirement is satisfied the capacitance is adequate for filtering. The steady-state output ripple (VOUT) is determined by: 1 VOUT IRIPPLE ESR + 8NfCOUT where f = operating frequency of each stage, N is the number of output stages, COUT = output capacitance and IL = ripple current in each inductor. The output ripple is highest at maximum input voltage since IL increases U with input voltage. The output ripple will be less than 50mV at max VIN with IL = 0.4IOUT(MAX) assuming: COUT required ESR < N * RSENSE and COUT > 1/(8Nf)(RSENSE) The emergence of very low ESR capacitors in small, surface mount packages makes very small physical implementations possible. The ability to externally compensate the switching regulator loop using the ITH pin allows a much wider selection of output capacitor types. The impedance characteristics of each capacitor type is significantly different than an ideal capacitor and therefore requires accurate modeling or bench evaluation during design. Manufacturers such as Nichicon, United Chemicon and Sanyo should be considered for high performance throughhole capacitors. The OS-CON semiconductor dielectric capacitor available from Sanyo and the Panasonic SP surface mount types have a good (ESR)(size) product. Once the ESR requirement for COUT has been met, the RMS current rating generally far exceeds the IRIPPLE(P-P) requirement. Ceramic capacitors from AVX, Taiyo Yuden, Murata and Tokin offer high capacitance value and very low ESR, especially applicable for low output voltage applications. In surface mount applications, multiple capacitors may have to be paralleled to meet the ESR or RMS current handling requirements of the application. Aluminum electrolytic and dry tantalum capacitors are both available in surface mount configurations. New special polymer surface mount capacitors offer very low ESR also but have much lower capacitive density per unit volume. In the case of tantalum, it is critical that the capacitors are surge tested for use in switching power supplies. Several excellent choices are the AVX TPS, AVX TPSV, the KEMET T510 3733i W UU 13 LTC3733/LTC3733-1 APPLICATIO S I FOR ATIO series of surface-mount tantalums or the Panasonic SP series of surface mount special polymer capacitors available in case heights ranging from 2mm to 4mm. Other capacitor types include Sanyo POS-CAP, Sanyo OS-CON, Nichicon PL series and Sprague 595D series. Consult the manufacturer for other specific recommendations. RSENSE Selection for Output Current Once the frequency and inductor have been chosen, RSENSE1, RSENSE2, RSENSE3 are determined based on the required peak inductor current. The current comparator has a maximum threshold of 75mV/RSENSE and an input common mode range of SGND to (1.1) * VCC. The current comparator threshold sets the peak inductor current, yielding a maximum average output current IMAX equal to the peak value less half the peak-to-peak ripple current, IL. Allowing a margin for variations in the IC and external component values yields: RSENSE = N 50mV IMAX The IC works well with values of RSENSE from 0.001 to 0.02. VCC Decoupling The VCC pin supples power not only the internal circuits of the controller but also the top and bottom gate drivers and therefore must be bypassed very carefully to ground with a ceramic capacitor, type X7R or X5R (depending upon the operating temperature environment) of at least 1F immediately next to the IC and preferably an additional 10F placed very close to the IC due to the extremely high instantaneous currents involved. The total capacitance, taking into account the voltage coefficient of ceramic capacitors, should be 100 times as large as the total combined gate charge capacitance of ALL of the MOSFETs being driven. Good bypassing close to the IC is necessary 14 U to supply the high transient currents required by the MOSFET gate drivers while keeping the 5V supply quiet enough so as not to disturb the very small-signal high bandwidth of the current comparators. Topside MOSFET Driver Supply (CB, DB) External bootstrap capacitors, CB, connected to the BOOST pins, supply the gate drive voltages for the topside MOSFETs. Capacitor CB in the Functional Diagram is charged though diode DB from VCC when the SW pin is low. When one of the topside MOSFETs turns on, the driver places the CB voltage across the gate-source of the desired MOSFET. This enhances the MOSFET and turns on the topside switch. The switch node voltage, SW, rises to VIN and the BOOST pin follows. With the topside MOSFET on, the boost voltage is above the input supply (VBOOST = VCC + VIN). The value of the boost capacitor CB needs to be 30 to 100 times that of the total input capacitance of the topside MOSFET(s). The reverse breakdown of DB must be greater than VIN(MAX). Differential Amplifier The IC has a true remote voltage sense capability. The sensing connections should be returned from the load, back to the differential amplifier's inputs through a common, tightly coupled pair of PC traces. The differential amplifier rejects common mode signals capacitively or inductively radiated into the feedback PC traces as well as ground loop disturbances. The differential amplifier output signal is divided down through the VID DAC and is compared with the internal, precision 0.6V voltage reference by the error amplifier. The amplifier has a 0 to VCC - 1.2V common mode input range and an output swing range of 0 to VCC - 1.2V. The output uses an NPN emitter follower with 80k feedback resistance. A DC resistive load to ground is required in order to sink more current. 3733i W UU LTC3733/LTC3733-1 APPLICATIO S I FOR ATIO Output Voltage The IC includes a digitally controlled 5-bit attenuator producing output voltages as defined in Table 1. Output voltages with 25mV increments are produced from 0.8V to 1.55V. Each VID digital input is pulled up to a logical high with an internal 150k resistor. The input logic threshold is approximately 1.2V but the input circuit can withstand an input voltage of up to 7V. ON/OFF Control The RUN pin provides simple ON/OFF control for the LTC3733. Driving the RUN pin above 1.5V permits the controller to start operating. Pulling RUN below 0.8V puts the LTC3733 into low current shutdown (IQ < 100A). Soft-Start Function The SS pin provides two functions: 1) soft-start and 2) a defeatable short-circuit latch off timer. Soft-start reduces the input power sources' surge currents by gradually increasing the controller's current limit (proportional to an internal buffered and clamped VITH). The latchoff timer prevents very short, extreme load transients from tripping the overcurrent latch. A small pull-up current (>5A) supplied to the SS pin will prevent the overcurrent latch from operating. The following explanation describes how this function operates. An internal 1.5A current source charges up the CSS capacitor. As the voltage on SS increases from 0V to 2.4V, the internal current limit is increased from 0V/RSENSE to 75mV/RSENSE. The output current limit ramps up slowly, taking 1s/F to reach full current. The output current thus ramps up slowly, eliminating the starting surge current required from the input power supply. tIRAMP = 2.4V - 0 V CSS = (1.6s/F) CSS 1.5A The SS pin has an internal 6V zener clamp (see the Functional Diagram). U Table 1. VID Output Voltage Programming VID4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 VID2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 VID1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 VID0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 VOUT 1.550 1.525 1.500 1.475 1.450 1.425 1.400 1.375 1.350 1.325 1.300 1.275 1.250 1.225 1.200 1.175 1.150 1.125 1.100 1.075 1.050 1.025 1.000 0.975 0.950 0.925 0.900 0.875 0.850 0.825 0.800 Shutdown 3733i W UU 15 LTC3733/LTC3733-1 APPLICATIO S I FOR ATIO Fault Conditions: Overcurrent Latchoff The SS pin also provides the ability to latch off the controllers when an overcurrent condition is detected. The SS capacitor is used initially to limit the inrush current of all three output stages. After the controllers have been given adequate time to charge up the output capacitor and provide full load current, the SS capacitor is used for a short-circuit timer. If the output voltage falls to less than 70% of its nominal value, the SS capacitor begins discharging on the assumption that the output is in an overcurrent condition. If the condition lasts for a long enough period, as determined by the size of the SS capacitor, the controller will be shut down until the RUN pin voltage is recycled. If the overload occurs during startup, the time can be approximated by: tLO1 >> (CSS * 0.6V)/(1.5A) = 4 * 105 (CSS) If the overload occurs after start-up, the voltage on the SS capacitor will continue charging and will provide additional time before latching off: tLO2 >> (CSS * 3V)/(1.5A) = 2 * 106 (CSS) This built-in overcurrent latchoff can be overridden by providing a pull-up resistor to the SS pin from VCC as shown in Figure 7. When VCC is 5V, a 200k resistance will prevent the discharge of the SS capacitor during an overcurrent condition but also shortens the soft-start period, so a larger SS capacitor value will be required. Why should you defeat overcurrent latchoff? During the prototyping stage of a design, there may be a problem with noise pick-up or poor layout causing the protection circuit VCC RSS SS PIN CSS 3733 F07 Figure 7. Defeating Overcurrent Latchoff 16 U to latch off the controller. Defeating this feature allows troubleshooting of the circuit and PC layout. The internal foldback current limiting still remains active, thereby protecting the power supply system from failure. A decision can be made after the design is complete whether to rely solely on foldback current limiting or to enable the latchoff feature by removing the pull-up resistor. The value of the soft-start capacitor CSS may need to be scaled with output current, output capacitance and load current characteristics. The minimum soft-start capacitance is given by: CSS > (COUT )(VOUT) (10 -4) (RSENSE) The minimum recommended soft-start capacitor of CSS = 0.1F will be sufficient for most applications. Current Foldback In certain applications, it may be desirable to defeat the internal current foldback function. A negative impedance is experienced when powering a switching regulator. That is, the input current is higher at a lower VIN and decreases as VIN is increased. Current foldback is designed to accommodate a normal, resistive load having increasing current draw with increasing voltage. The EAIN pin should be artificially held 70% above its nominal operating level of 0.6V, or 0.42V in order to prevent the IC from "folding back" the peak current level. A suggested circuit is shown in Figure 8. VCC VCC LTC3733 Q1 CALCULATE FOR 0.42V TO 0.55V EAIN 3733 F08 W UU Figure 8. Foldback Current Elimination 3733i LTC3733/LTC3733-1 APPLICATIO S I FOR ATIO The emitter of Q1 will hold up the EAIN pin to a voltage in the absence of VOUT that will prevent the internal sensing circuitry from reducing the peak output current. Removing the function in this manner eliminates the external MOSFET's protective feature under short-circuit conditions. This technique will also prevent the short-circuit latchoff function from turning off the part during a shortcircuit event and the output current will only be limited to N * 75mV/RSENSE. Undervoltage Reset In the event that the input power source to the IC (VCC) drops below 4V, the SS capacitor will be discharged to ground and the controller will be shut down. When VCC rises above 4V, the SS capacitor will be allowed to recharge and initiate another soft-start turn-on attempt. This may be useful in applications that switch between two supplies that are not diode connected, but note that this cannot make up for the resultant interruption of the regulated output. Phase-Locked Loop and Frequency Synchronization (LTC3733-1) The IC has a phase-locked loop comprised of an internal voltage controlled oscillator and phase detector. This allows the top MOSFET of output stage 1's turn-on to be locked to the rising edge of an external source. The frequency range of the voltage controlled oscillator is 50% around the center frequency fO. A voltage applied to the PLLFLTR pin of 1.2V corresponds to a frequency of approximately 350kHz. The nominal operating frequency range of the IC is 210kHz to 530kHz. The phase detector used is an edge sensitive digital type that provides zero degrees phase shift between the external and internal oscillators. This type of phase detector will not lock the internal oscillator to harmonics of the input frequency. The PLL hold-in range, fH, is equal to the capture range, fC: fH = fC = 0.5 fO U The output of the phase detector is a complementary pair of current sources charging or discharging the external filter components on the PLLFLTR pin. A simplified block diagram is shown in Figure 9. If the external frequency (fPLLIN) is greater than the oscillator frequency, fOSC, current is sourced continuously, pulling up the PLLFLTR pin. When the external frequency is less than fOSC, current is sunk continuously, pulling down the PLLFLTR pin. If the external and internal frequencies are the same, but exhibit a phase difference, the current sources turn on for an amount of time corresponding to the phase difference. Thus, the voltage on the PLLFLTR pin is adjusted until the phase and frequency of the external and internal oscillators are identical. At this stable operating point, the phase comparator output is open and the filter capacitor CLP holds the voltage. The IC PLLIN pin must be driven from a low impedance source such as a logic gate located close to the pin. When using multiple ICs for a phase-locked system, the PLLFLTR pin of the master oscillator should be biased at a voltage that will guarantee the slave oscillator(s) ability to lock onto the master's frequency. A voltage of 1.7V or below applied to the master oscillator's PLLFLTR pin is recommended in order to meet this requirement. The resultant operating frequency will be approximately 500kHz for 1.7V. PHASE DETECTOR/ OSCILLATOR 2.4V RLP 10k CLP PLLFLTR PLLIN (LTC3733-1 ONLY) 50k DIGITAL PHASE/ FREQUENCY DETECTOR EXTERNAL OSC OSC 3733 F09 W UU Figure 9. Phase-Locked Loop Block Diagram 3733i 17 LTC3733/LTC3733-1 APPLICATIO S I FOR ATIO The loop filter components (CLP, RLP) smooth out the current pulses from the phase detector and provide a stable input to the voltage controlled oscillator. The filter components CLP and RLP determine how fast the loop acquires lock. Typically RLP =10k and CLP ranges from 0.01F to 0.1F. Minimum On-Time Considerations Minimum on-time, tON(MIN), is the smallest time duration that the IC is capable of turning on the top MOSFET. It is determined by internal timing delays and the gate charge of the top MOSFET. Low duty cycle applications may approach this minimum on-time limit and care should be taken to ensure that: tON(MIN) < VOUT VIN ( f) If the duty cycle falls below what can be accommodated by the minimum on-time, the IC will begin to skip every other cycle, resulting in half-frequency operation. The output voltage will continue to be regulated, but the ripple current and ripple voltage will increase. The minimum on-time for the IC is generally about 120ns. However, as the peak sense voltage decreases the minimum on-time gradually increases. This is of particular concern in forced continuous applications with low ripple current at light loads. If the duty cycle drops below the minimum on-time limit in this situation, a significant amount of cycle skipping can occur with correspondingly larger current and voltage ripple. If an application can operate close to the minimum ontime limit, an inductor must be chosen that is low enough in value to provide sufficient ripple amplitude to meet the minimum on-time requirement. As a general rule, keep the inductor ripple current equal to or greater than 30% of IOUT(MAX) at VIN(MAX). 18 U Efficiency Considerations The percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Percent efficiency can be expressed as: %Efficiency = 100% - (L1 + L2 + L3 + ...) where L1, L2, etc. are the individual losses as a percentage of input power. Checking Transient Response The regulator loop response can be checked by looking at the load transient response. Switching regulators take several cycles to respond to a step in DC (resistive) load current. When a load step occurs, VOUT shifts by an amount equal to ILOAD * ESR, where ESR is the effective series resistance of COUT. ILOAD also begins to charge or discharge COUT, generating the feedback error signal that forces the regulator to adapt to the current change and return VOUT to its steady-state value. During this recovery time, VOUT can be monitored for excessive overshoot or ringing, which would indicate a stability problem. The availability of the ITH pin not only allows optimization of control loop behavior, but also provides a DC coupled and AC filtered closed-loop response test point. The DC step, rise time and settling at this test point truly reflects the closed-loop response. Assuming a predominantly second order system, phase margin and/or damping factor can be estimated using the percentage of overshoot seen at this pin. The bandwidth can also be estimated by examining the rise time at the pin. The ITH external components shown in the Figure 1 circuit will provide an adequate starting point for most applications. 3733i W UU LTC3733/LTC3733-1 APPLICATIO S I FOR ATIO The ITH series RC-CC filter sets the dominant pole-zero loop compensation. The values can be modified slightly (from 0.2 to 5 times their suggested values) to maximize transient response once the final PC layout is done and the particular output capacitor type and value have been determined. The output capacitors need to be decided upon because the various types and values determine the loop feedback factor gain and phase. An output current pulse of 20% to 80% of full load current having a rise time of <2s will produce output voltage and ITH pin waveforms that will give a sense of the overall loop stability without breaking the feedback loop. The initial output voltage step, resulting from the step change in output current, may not be within the bandwidth of the feedback loop, so this signal cannot be used to determine phase margin. This is why it is better to look at the ITH pin signal which is in the feedback loop and is the filtered and compensated control loop response. The gain of the loop will be increased by increasing RC and the bandwidth of the loop will be increased by decreasing CC. If RC is increased by the same factor that CC is decreased, the zero frequency will be kept the same, thereby keeping the phase the same in the most critical frequency range of the feedback loop. The output voltage settling behavior is related to the stability of the closed-loop system and will demonstrate the actual overall supply performance. A second, more severe transient is caused by switching in loads with large (>1F) supply bypass capacitors. The discharged bypass capacitors are effectively put in parallel with COUT, causing a rapid drop in VOUT. No regulator can alter its delivery of current quickly enough to prevent this sudden step change in output voltage if the load switch resistance is low and it is driven quickly. If CLOAD is greater than 2% of COUT , the switch rise time should be controlled so that the load rise time is limited to approximately 1000 * RSENSE * CLOAD. Thus a 250F capacitor and a 2m U RSENSE resistor would require a 500s rise time, limiting the charging current to about 1A. Design Example (Using Three Phases) As a design example, assume VIN = 12V(nominal), VIN = 20V(max), VOUT = 1.3V, IMAX = 45A and f = 400kHz. The inductance value is chosen first based upon a 30% ripple current assumption. The highest value of ripple current in each output stage occurs at the maximum input voltage. W UU L= = VOUT VOUT 1- f( I) VIN 1.3V 1.3V 1- (400kHz)(30%)(15A) 20V 0.68H Using L = 0.6H, a commonly available value results in 34% ripple current. The worst-case output ripple for the three stages operating in parallel will be less than 11% of the peak output current. RSENSE1, RSENSE2 and RSENSE3 can be calculated by using a conservative maximum sense current threshold of 65mV and taking into account half of the ripple current: RSENSE = 65mV = 0.0037 34% 15A 1 + 2 Use a commonly available 0.003 sense resistor. Next verify the minimum on-time is not violated. The minimum on-time occurs at maximum VCC: tON(MIN) = VIN(MAX) ( f) VOUT = 1.3V = 162ns 20 V(400kHz) 3733i 19 LTC3733/LTC3733-1 APPLICATIO S I FOR ATIO The output voltage will be set by the VID code according to Table 1. The power dissipation on the topside MOSFET can be estimated. Using a Fairchild FDS6688 for example, RDS(ON) = 7m, CMILLER = 15nC/15V = 1000pF. At maximum input voltage with T(estimated) = 50C: PMAIN 1.8 V (15)2 1+ (0.005)(50C - 25C) 20 V 2 45A 0.007 + (20) (2)(1000pF ) (2)(3) 1 1 + (400kHz) = 2.2W 5V - 1.8 V 1.8 V The worst-case power dissipation by the synchronous MOSFET under normal operating conditions at elevated ambient temperature and estimated 50C junction temperature rise is: PSYNC = 20 V - 1.3V (15A)2 (1.25)(0.007) = 1.84W 20 V [ A short circuit to ground will result in a folded back current of: 25mV 1 150ns(20 V ) ISC + = 7.5A (2 + 3)m 2 0.6H with a typical value of RDS(ON) and d = (0.005/C)(50C) = 0.25. The resulting power dissipated in the bottom MOSFET is: PSYNC = (7.5A)2(1.25)(0.007) 0.5W which is less than one third of the normal, full load conditions. Incidentally, since the load no longer dissipates any power, total system power is decreased by over 90%. Therefore, the system actually cools significantly during a shorted condition! PC Board Layout Checklist When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the 20 U IC. These items are also illustrated graphically in the layout diagram of Figure 10. Check the following in the PC layout: 1) Are the signal and power ground paths isolated? Keep the SGND at one end of a printed circuit path thus preventing MOSFET currents from traveling under the IC. The IC signal ground pin should be used to hook up all control circuitry on one side of the IC, routing the copper through SGND, under the IC covering the "shadow" of the package, connecting to the PGND pin and then continuing on to the (-) plates of CIN and COUT. The VCC decoupling capacitor should be placed immediately adjacent to the IC between the VCC pin and PGND. A 1F ceramic capacitor of the X7R or X5R type is small enough to fit very close to the IC to minimize the ill effects of the large current pulses drawn to drive the bottom MOSFETs. An additional 5F to 10uF of ceramic, tantalum or other very low ESR capacitance is recommended in order to keep the internal IC supply quiet. The power ground returns to the sources of the bottom N-channel MOSFETs, anodes of the Schottky diodes and (-) plates of CIN, which should have as short lead lengths as possible. 2) Does the IC IN+ pin connect to the (+) plates of COUT? A 30pF to 300pF feedforward capacitor between the DIFFOUT and EAIN pins should be placed as close as possible to the IC. 3) Are the SENSE- and SENSE+ printed circuit traces for each channel routed together with minimum PC trace spacing? The filter capacitors between SENSE+ and SENSE- for each channel should be as close as possible to the pins of the IC. Connect the SENSE- and SENSE+ pins to the pads of the sense resistor as illustrated in Figure 11. 4) Do the (+) plates of CIN connect to the drains of the topside MOSFETs as closely as possible? This capacitor provides the pulsed current to the MOSFETs. 5) Keep the switching nodes, SWITCH, BOOST and TG away from sensitive small-signal nodes. Ideally the SWITCH, BOOST and TG printed circuit traces should be routed away and separated from the IC and the "quiet" side of the IC. 6) The filter capacitors between the ITH and SGND pins should be as close as possible to the pins of the IC. W UU ] 3733i LTC3733/LTC3733-1 APPLICATIO S I FOR ATIO SW1 VIN SW1 RIN + CIN D1 COUT BOLD LINES INDICATE HIGH, SWITCHING CURRENT LINES. KEEP LINES TO A MININMUM LENGTH SW2 Figure 10. Branch Current Waveforms INDUCTOR LTC3733 SENSE+ SENSE- 1000pF Figure 11. Kelvin Sensing RSENSE 3733i U L1 RSENSE1 D1 L1 RSENSE1 VOUT W UU + RL L2 RSENSE2 D2 3732 F10 SENSE RESISTOR 3733 F11 OUTPUT CAPACITOR 21 LTC3733/LTC3733-1 APPLICATIO S I FOR ATIO Figure 10 illustrates all branch currents in a three-phase switching regulator. It becomes very clear after studying the current waveforms why it is critical to keep the high switching current paths to a small physical size. High electric and magnetic fields will radiate from these "loops" just as radio stations transmit signals. The output capacitor ground should return to the negative terminal of the input capacitor and not share a common ground path with any switched current paths. The left half of the circuit gives rise to the "noise" generated by a switching regulator. The ground terminations of the synchronous MOSFETs and Schottky diodes should return to the bottom plate(s) of the input capacitor(s) with a short isolated PC trace since very high switched currents are present. A separate isolated path from the bottom plate(s) of the input and output capacitor(s) should be used to tie in the IC power ground pin (PGND). This technique keeps inherent signals generated by high current pulses taking alternate current paths that have SW V ICIN ICOUT SW1 V SW2 V SW3 V IL1 IL2 IL3 ICIN ICOUT 3732 F12 Figure 12. Single and Polyphase Current Waveforms 22 U finite impedances during the total period of the switching regulator. External OPTI-LOOP compensation allows overcompensation for PC layouts which are not optimized but this is not the recommended design procedure. Simplified Visual Explanation of How a 3-Phase Controller Reduces Both Input and Output RMS Ripple Current The effect of multiphase power supply design significantly reduces the amount of ripple current in both the input and output capacitors. The RMS input ripple current is divided by, and the effective ripple frequency is multiplied up by the number of phases used (assuming that the input voltage is greater than the number of phases used times the output voltage). The output ripple amplitude is also reduced by, and the effective ripple frequency is increased by the number of phases used. Figure 12 graphically illustrates the principle. SINGLE PHASE TRIPLE PHASE 3733i W UU LTC3733/LTC3733-1 APPLICATIO S I FOR ATIO The worst-case input RMS ripple current for a single stage design peaks at twice the value of the output voltage. The worst-case input RMS ripple current for a two stage design results in peaks at 1/4 and 3/4 of the input voltage, and the worst-case input RMS ripple current for a three stage design results in peaks at 1/6, 1/2, and 5/6 of the input voltage. The peaks, however, are at ever decreasing levels with the addition of more phases. A higher effective duty factor results because the duty factors "add" as long as the currents in each stage are balanced. Refer to AN19 for a detailed description of how to calculate RMS current for the single stage switching regulator. Figure 6 illustrates the RMS input current drawn from the input capacitance versus the duty cycle as determined by the ration of input and output voltage. The peak input RMS current level of the single phase system is reduced by 2/3 in a 3-phase solution due to the current splitting between the three stages. The output ripple current is reduced significantly when compared to the single phase solution using the same inductance value because the VOUT/L discharge currents term from the stages that has their bottom MOSFETs on subtract current from the (VCC - VOUT)/L charging current resulting from the stage which has its top MOSFET on. The output ripple current for a 3-phase design is: IP-P = VOUT (1- 3DC) VIN > 3VOUT ( f)(L) The ripple frequency is also increased by three, further reducing the required output capacitance when VCC < 3VOUT as illustrated in Figure 4. U Efficiency Calculation To estimate efficiency, the DC loss terms include the input and output capacitor ESR, each MOSFET RDS(ON), inductor resistance RL, the sense resistance RSENSE and the forward drop of the Schottky rectifier at the operating output current and temperature. Typical values for the design example given previously in this data sheet are: Main MOSFET RDS(ON) = 7m (9m at 90C) Sync MOSFET RDS(ON) = 7m (9m at 90C) CINESR = 20m COUTESR = 3m RL = 2.5m RSENSE = 3m VSCHOTTKY = 0.8V at 15A (0.7V at 90C) VOUT = 1.3V VIN = 12V IMAX = 0.8V at 15A (0.7V at 90C) = 0.01%C N=3 f = 400kHz The main MOSFET is on for the duty factor VOUT/VIN and the synchronous MOSFET is on for the rest of the period or simply (1 - VOUT/VIN). Assuming the ripple current is small, the AC loss in the inductor can be made small if a good quality inductor is chosen. The average current, IOUT is used to simplify the calaculations. The equation below is not exact but should provide a good technique for the comparison of selected components and give a result that is within 10% to 20% of the final application. 3733i W UU 23 LTC3733/LTC3733-1 APPLICATIO S I FOR ATIO The temperature of the MOSFET's die temperature may require interative calculations if one is not familiar typical performance. A maximum operating junction temperature of 90 to 100C for the MOSFETs is recommended for high reliability applications. Common output path DC loss: I PCOMPATH N MAX (RL + RSENSE ) + COUTESR Loss N 2 This totals 3.375W + COUTESR loss. Total of all three main MOSFET's DC loss: V I PMAIN = N OUT MAX (1 + )RDS(ON) + CINESR Loss VIN N 2 This totals 0.83W + CINESR loss. Total of all three synchronous MOSFET's DC loss: V I PSYNC = N 1 - OUT MAX (1 + )RDS(ON) VIN N 2 This totals 5.4W. Total of all three main MOSFET's AC loss: 45A PMAIN 3( VIN )2 (2)(1000pF) (2)(3) 1 1 + (400kHz) = 6.3W 5V - 1.8 V 1.8 V This totals 1W at VIN = 8V, 2.25W at VIN = 12V and 6.25W at VIN = 20V. 24 U Total of all three synchronous MOSFET's AC loss: W UU (3)QG VIN VDSSPEC ( f) = (6)(15nC) VIN VDSSPEC (4E5) This totals 0.08W at VIN = 8V, 0.12W at VIN = 12V and 0.19W at VIN = 20V. The bottom MOSFET does not experience the Miller capacitance dissipation issue that the main switch does because the bottom switch turns on when its drain is close to ground. The Schottky rectifier loss assuming 50ns nonoverlap time: 2 * 3(0.7V)(15A)(50ns)(4E5) This totals 1.26W. The total output power is (1.3V)(45A) = 58.5W and the total input power is approximately 60W so the % loss of each component is as follows: Main switch AC loss (VIN = 12V) Main switch DC loss Synchronous switch AC loss Synchronous switch DC loss Power path loss 2.25W 0.83W 0.19W 5.4W 3.75% 1.4% 0.3% 9% 3.375W 5.6% The numbers above represent the values at VIN = 12V. It can be seen from this simple example that two things can be done to improve efficiency: 1) Use two MOSFETs on the synchronous side and 2) use a smaller MOSFET for the main switch with smaller CMILLER to better balance the AC loss with the DC loss. A smaller, less expensive MOSFET can actually perform better in the task of the main switch. 3733i LTC3733/LTC3733-1 TYPICAL APPLICATIO VCC 51k VID1 IN 10k ON/OFF 1 2 3 4 VID1 RUN PLLFLTR FCB IN+ 100pF 5 6 30pF 7 8 9 S1+ 71.5k 1000pF S1- S2+ 1000pF S2- S3- 1000pF S3+ 180pF 0.1F 10 11 12 13 14 15 16 17 VID2 IN 18 SW1 LTC3733 - BOOST2 IN DIFFOUT EAIN SGND SENSE1+ SENSE1- SENSE2+ SENSE2- SENSE3- SENSE3+ SS ITH VID2 TG2 SW2 VCC BG1 PGND BG2 BG3 SW3 TG3 BOOST3 VID4 VID3 5V 22.1k 100pF 15k VIN: 7V TO 21V VOUT: 0.8V TO 1.55V, 65A SWITCHING FREQUENCY: 300kHz CIN: SANYO OS-CON 25SP68M COUT: 330F/2.5V x10 SANYO POSCAP 2R5TPE330M9 D1 TO D3: MBRS340T3 DIFFOUT VIN CLK 60 EAIN IN+ PLLIN 3-PHASE LTC3733-1 3733 TA02 IN- ITH U 65A Power Supply for AMD Opteron Processors VCC VID0 PGOOD BOOST1 TG1 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 0.1F VID4 IN VID3 IN 3733 TA01 PGOOD 47k 1 M1 VCC VCC 5V VIN L1 0.002 10F 6.3V x3 VID0 IN 0.1F VOUT + COUT M2 D1 0.1F VIN M3 1F 10F M4 D2 L2 S1+ S1- 0.002 10F 35V x5 + VIN CIN 7V TO 21V 68F 25V S2+ S2- VIN M5 L3 D3 S3+ VCC L1 TO L3: 0.68H SUMIDA CEP125-0R6 M1, M3, M5: IRF7811W x2 OR FDS6682 x2 OR Si7860DP x1 M2, M4, M6: IRF7822 x2 OR Si7892DP x2 S3- 0.002 M6 Block Diagram--6-Phase LTC3731/LTC3733-1 Supply 3-PHASE LTC3731 CLKOUT VOUT 0.8V TO 1.55V 90A TO 120A 3733i 25 LTC3733/LTC3733-1 PACKAGE DESCRIPTIO 5.20 - 5.38** (.205 - .212) .13 - .22 (.005 - .009) .55 - .95 (.022 - .037) NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS MILLIMETERS 2. DIMENSIONS ARE IN (INCHES) 3. DRAWING NOT TO SCALE *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED .152mm (.006") PER SIDE **DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE 26 U G Package 36-Lead Plastic SSOP (5.3mm) (Reference LTC DWG # 05-08-1640) 12.67 - 12.93* (.499 - .509) 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 7.65 - 7.90 (.301 - .311) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1.73 - 1.99 (.068 - .078) 0 - 8 .65 (.0256) BSC .25 - .38 (.010 - .015) .05 - .21 (.002 - .008) G36 SSOP 0501 3733i LTC3733/LTC3733-1 PACKAGE DESCRIPTIO 5.50 0.05 (2 SIDES) 4.10 0.05 (2 SIDES) 3.20 0.05 (2 SIDES) 5.00 0.10 (2 SIDES) PIN 1 TOP MARK (SEE NOTE 6) 7.00 0.10 (2 SIDES) 0.75 0.05 NOTE: 1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE M0-220 VARIATION WHKD 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS U UHF Package 38-Lead Plastic QFN (7mm x 5mm) (Reference LTC DWG # 05-08-1701) 0.70 0.05 PACKAGE OUTLINE 0.25 0.05 0.50 BSC 5.20 0.05 (2 SIDES) 6.10 0.05 (2 SIDES) 7.50 0.05 (2 SIDES) RECOMMENDED SOLDER PAD LAYOUT 0.75 0.05 0.00 - 0.05 3.15 0.10 (2 SIDES) 0.435 0.18 0.18 37 38 1 2 0.23 5.15 0.10 (2 SIDES) 0.40 0.10 0.200 REF 0.25 0.05 0.200 REF 0.00 - 0.05 0.50 BSC R = 0.115 TYP (UH) QFN 0303 BOTTOM VIEW--EXPOSED PAD 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 3733i 27 LTC3733/LTC3733-1 RELATED PARTS DESCRIPTION High Power Step-Down Synchronous DC/DC Controller in SO-8 LTC1628/LTC1628-PG/ 2-Phase, Dual Output Synchronous Step-Down LTC1628-SYNC DC/DC Controllers LTC1629/ 20A to 200A PolyPhase Synchronous Controllers LTC1629-PG LTC1702 No RSENSETM 2-Phase Dual Synchronous Step-Down Controller LTC1703 No RSENSE 2-Phase Dual Synchronous Step-Down Controller with 5-Bit Mobile VID Control LTC1708-PG 2-Phase, Dual Synchronous Controller with Mobile VID LT(R)1709/ High Efficiency, 2-Phase Synchronous Step-Down LT1709-8 Switching Regulators with 5-Bit VID LTC1735 High Efficiency Synchronous Step-Down Switching Regulator LTC1736 High Efficiency Synchronous Controller with 5-Bit Mobile VID Control LTC1778 No RSENSE Current Mode Synchronous Step-Down Controller LTC1929/ 2-Phase Synchronous Controllers LTC1929-PG LTC3711 No RSENSE Current Mode Synchronous Step-Down Controller with Digital 5-Bit Interface LTC3719 2-Phase, 5-Bit VID Current Mode, High Efficiency Synchronous Step-Down Controller LTC3729 20A to 200A, 550kHz PolyPhase Synchronous Controller LTC3731 PART NUMBER LTC1530 COMMENTS High Efficiency 5V to 3.3V Conversion at Up to 15A Reduces CIN and COUT, Power Good Output Signal, Synchronizable, 3.5V VIN 36V, IOUT up to 20A, 0.8V VOUT 5V Expandable from 2-Phase to 12-Phase, Uses All Surface Mount Components, No Heat Sink, VIN up to 36V 550kHz, No Sense Resistor Mobile Pentium(R) III Processors, 550kHz, VIN 7V 3.5V VIN 36V, VID Sets VOUT1, PGOOD 1.3V VOUT 3.5V, Current Mode Ensures Accurate Current Sharing, 3.5V VIN 36V Output Fault Protection, 16-Pin SSOP Output Fault Protection, 24-Pin SSOP, 3.5V VIN 36V Up to 97% Efficiency, 4V VIN 36V, 0.8V VOUT (0.9)(VIN), IOUT up to 20A Up to 42A, Uses All Surface Mount Components, No Heat Sinks, 3.5V VIN 36V Up to 97% Efficiency, Ideal for Pentium III Processors, 0.925V VOUT 2V, 4V VIN 36V, IOUT up to 20A AMD Hammer-K8 Processors, Wide VIN Range: 4V to 36V Operation Expandable from 2-Phase to 12-Phase, Uses all Surface Mount Components, VIN up to 36V Expandable from 3-Phase to 12-Phase, Uses all Surface Mount Components, VIN up to 36V VRM9.0 and VRM9.1 (VID = 1.1V to 1.85V) 3-Phase, 600kHz Synchronous Buck Switching Regulator Controller LTC3732 3-Phase, 5-Bit VID, 600kHz Synchronous Buck Switching Regulator Controller No RSENSE is a trademark of Linear Technology Corporation. Pentium is a registered trademark of Intel Corporation. 3733i 28 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 q FAX: (408) 434-0507 q LT/TP 0603 1K * PRINTED IN USA www.linear.com (c) LINEAR TECHNOLOGY CORPORATION 2003 |
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